Matching Items (4)
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- All Subjects: Built-In Self-Test
- Creators: Ozev, Sule
Description
Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed.
Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced.
Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method.
Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed.
Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.
Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced.
Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method.
Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed.
Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.
ContributorsJeong, Jae Woong (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
As integrated technologies are scaling down, there is an increasing trend in the
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
ContributorsShafiee, Maryam (Author) / Ozev, Sule (Thesis advisor) / Diaz, Rodolfo (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2018
Description
Recent advancements in communication standards, such as 5G demand transmitter hardware to support high data rates with high energy efficiency. With the revolution of communication standards, modulation schemes have become more complex and require high peak-to-average (PAPR) signals. In wireless transceiver hardware, the power amplifier (PA) consumes most of the transceiver’s DC power and is typically the bottleneck for transmitter linearity. Therefore, the transmitter’s performance directly depends on the PA. To support high PAPR signals, the PA must operate efficiently at its saturated and backoff output power. Maintaining high efficiency at both peak and backoff output power is challenging. One effective technique for addressing this problem is load modulation. Some of the prominent load-modulated PA architectures are outphasing PAs, load-modulated balanced amplifiers (LMBA), envelope elimination and restoration (EER), envelope tracking (ET), Doherty power amplifiers (DPA), and polar transmitters. Amongst them, the DPA is the most popular for infrastructure applications due to its simpler architecture compared to other techniques and linearizability with digital pre-distortion (DPD). Another crucial characteristic of progressing communication standards is wide signal bandwidths. High-efficiency power amplifiers like class J/F/F-1 and load-modulated PAs like the DPA exhibit narrowband performance because the amplifiers require precise output impedance terminations. Therefore, it is equally essential to develop adaptable PA solutions to process radio frequency (RF) signals with wide bandwidths. To support modern and future cellular infrastructure, RF PAs need to be innovated to increase the backoff power efficiency by two times or more and support ten times or more wider bandwidths than current state-of-the-art PAs. This work presents five RF PA analyses and implementations to support future wireless communications transmitter hardware. Chapter 2 presents an optimized output-matching network analysis and design to achieve extended output power backoff of the DPA. Chapters 3 and 4 unveil two bandwidth enhancement techniques for the DPA while maintaining extended output power backoff. Chapter 5 exhibits a dual-band hybrid mode PA design targeted for wideband applications. Chapter 6 presents a built-in self-test circuit integrated into a PA for output impedance monitoring. This can alleviate the PA performance degradation due to the variation in the PA's output load over frequency, process, and aging. All RF PAs in this dissertation are implemented using Gallium Nitride (GaN)-based high electron mobility transistors (HEMT), and the realized designs validate the proposed PAs' theories/architectures.
ContributorsRoychowdhury, Debatrayee (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Aberle, James (Committee member) / Arizona State University (Publisher)
Created2024
Description
Designing a chip from a system-level packaged silicon die involves an intricate process aimed at ensuring functionality, performance, and reliability before
the chip is delivered to the end user. During fabrication, process variations and defects
that occur may result in unacceptable performance for the chip. Fabricated chips
undergo extensive testing to ensure they meet system specifications and are free of
defects. However, analog and radio frequency (RF) circuits are challenging and
expensive to test due to their sensitivity to process variations, slower test times in
comparison to digital circuits, sophisticated requirements, and the need for expensive,
high-performance equipment.
To address these challenges, a robust and low-cost structural Built-In Self-Test
(BIST) method is proposed to verify analog and RF circuits. This method of BIST can
reduce test development complexity, reduce reliance on automated test equipment
(ATE), lower area overhead, and ultimately improve product quality. The proposed
method depends on perturbing an analog or RF circuit with a stimulus at an injection
point, and observing the result at an observation point as a digitally measurable time
delay. Injection points within the circuit can be the primary input, an internal output, a
bias point for the circuit, an internal output, or the output of the circuit: essentially a
location where the stimulus will travel structurally through the circuit. Injection can
be achieved through a simple ON/OFF keying. Multiple injection points can be
enabled at a low cost (single transistor) while the observation circuit can be shared
among many injection points.
ContributorsJanssen, Samantha Mae (Author) / Ozev, Sule (Thesis advisor) / Hwang, Leslie (Committee member) / Zhang, Jeff (Committee member) / Arizona State University (Publisher)
Created2025